This invention relates to the field of microprocessor powered computers for video games and personal computers, incorporating DMA techniques, especially such systems which are implemented in MOS (metal oxide semiconductor) LSI (large scale integrated) circuitry where circuit area is a consideration. The invention further relates to enhanced systems where auxiliary circuitry has been added to the host system; where a television-type display device is used; and where bit map mode (at least one bit of video information is stored in memory for every element location (pixel) of the picture displayed) is likewise incorporated.
The invention also relates to video display drives for color video display monitors where color sprites (which are sometimes
Bit mapping, while space and time implementation consuming, has proven to be a straightforward and an accurate method for video display generation. Complex displays provided by video games and personal computers require overlay presentations of movable and/or changeable information and of fixed information; and of collisions between movable objects. Bit map implementation has been the focus of various prior circuits.
Prior video game circuits have provided a complex display format to a television receiver display unit (a cathode ray tube), which display unit generates the presentation with a plurality of horizontal scans or raster lines. A video game circuit which is capable of displaying fixed objects as background, as well as moving objects, is shown by Rosenthal, U.S. Pat. No. 4,053,740.
Rosenthal has built a special purpose digital computer to generate video game information from a plurality of selected, on a mutually exclusive basis, software defined programs. Operator commands are separated into an independent computational section and an independent display section of the circuit for processing. Rosenthal, U.S. Pat. No. 4,053,740, utilized arithmetic logic units to drive accumulators to control x and y registers and associated horizontal and vertical beam direction drive circuits for cathode ray tube displays.
Personal computers, such as the Apple Computer, have utilized a main microprocessor to perform computational operations and to process (retrieve) video display information to generate displays to a television-type receiver.
The Apple Computer has incorporated a general purpose microprocessor, the MOS Technology Inc. Model 6502, to perform both computational operations and video display information retrieval. Such a single microprocessor driven system has speed limitations, as most microprocessors, including the Model 6502, have significant processing dead time used for refreshing registers and resetting and initializing operations. As a result, information processing in such systems can be slow.
In order to enhance processing speeds these small microprocessor driven computers have sacrificed display quality, i.e., "definition", "character" and "detail."
One approach to increasing the speed of such a personal computer has been to utilize two processors; a Motorola Inc. 68000 and a 6502. In this system, the first processor is dedicated to computational operations and the second microprocessor is dedicated to video display information retrieval.
Other early game circuits, such as Dash et al., U.S. Pat. No. 4,034,983 utilized special purpose control circuits to generate signals to the antenna connection of a commercial color television receiver. Such a special purpose control circuit could include analog interface circuits for processing game-paddle signals and decoding functions, and sync pulse generation could be used to generate horizontal sync and raster scan information.
Personal computer and microprocessor driven systems, such as Chung, U.S. Pat. No. 4,177,462, have used display generator circuitry driven off of an address bus, data bus and control bus, including raster line generation and vertical position counters.
Likewise, Sukonick et al., U.S. Pat. No. 4,070,710 discloses incorporating video control circuits and raster memory access into a system with data and address bus architecture. Sukonick et al. discloses a video control circuit which relies upon a plurality of vertical and horizontal position registers, a skip pattern memory and modulo comparison circuitry for "FIFO" processing of video information.
Sukonick et al., U.S. Pat. No. 4,070,710, shows a two processor system. Sukonick et al. has added a display system 16 to his programmed host computer 10. This video display system 16 contains an Intel Corporation 8088 microprocessor 76 within the micro-control unit of the video display system.
Along this line Burson, U.S. Pat. No. 4,180,805, has provided a video display circuit which incorporates a general purpose microprocessor 15, the TMS 1100 microcomputer. A character memory is provided separate from a display memory and character generator memory. Each display memory word is partitioned into two bytes, with the first byte being a character memory address and the second of which being a sub-address to locate a character-word within a set of character words in memory. Each character memory word is likewise partitioned into two bytes with the first byte determining color and the second byte selecting a particular character from a prestored set.
The use of a second general purpose commercially available microcomputer to process video display information, while increasing the system speed, also increases the cost of manufacture for the system, as well as the size of the system, i.e., chip "real estate."
A micro control unit is also used and is necessary to the circuitry. The micro-control unit decodes instructions from a host computer for use by the raster memory unit and generates (encodes) control information to cause the raster memory to write display information, as well as to control the video control circuit to read information from the raster memory and to translate it into video signals usable by a CRT drive circuit. Ackley et al., U.S. Pat. No. 4,243,984, show a video display processor including general circuit components for overlay control, priority selection, sequence control, and memory control of sprite position and color.
Rahman, U.S. Pat. No. 4,420,770, shows a video background generation system including field correction logic, priority encoder circuitry and horizontal and vertical bit map memory.
Others have developed display circuits which have included an address bus, data bus, and control signal lines for interfacing with a microprocessor based computer system. Some display circuits have included DMA control and playfield and sprite-generator components utilizing a plurality of control registers connected to operate with a plurality of memories, including collision detection and display priority logic.
Dual commercial microprocessor systems have increased off-chip wire connections as each commercial circuit comes as a separate dual-in-line package (DIP). In LSI (large scale integration) circuit design, this increases backplane and circuit card costs and increases the likelihood of noise pickup, often necessitating additional filtering and increased signal levels, which usually leads to more power consumption. Except in the very expensive dual microprocessor systems--priced above the personal computer market--display quality is not greatly enhanced with these second microprocessors as noise pickup and filtering costs often dictate a lesser display output quality.
Others have taken a divergent and different approach, such as using a display generator circuit designed as a raster scan line buffer structure. In such an approach, a general microprocessor can be used to address display object storage random access memory (RAM). The circuitry divides the display into moving objects (sprites) and into stationary objects (playfields).
This approach, while cheaper to implement than the dual microprocessor approaches discussed above, and using less chip geometry and inter-chip wiring, does provide degraded system performance and display capabilities compared with the dual microprocessor systems.
One specific display generator enhanced microprocessor based system is shown by Hogan et al., U.S. Pat. No. 3,996,585, where a display generator is implemented with a plurality of buffer registers. He uses this display generator to process bit map information obtained from random access memory (RAM). A pattern generator is used to decode data for each raster scan line. Decoded rastor line data is stored in a buffer register for display. The pattern generator also decodes control data to determine collisons. The decoded collison control data is stored in a buffer register. Hogan et al.'s circuit is intended to relieve the system microprocessor from simple video display data retrieval and manipulation.
In keeping with the display generator circuit approach of Hogan et al., others have built a decoder based video display generators. Such a circuit would not utilize a second general purpose microprocessor to drive a video generator, but may use display instruction decoder circuits to provide movable object and stationary playfield object information to the video display, thereby reducing the work on the only (general purpose) microprocessor present. Any of these circuits, as with Hogan et al., require an increase in memory or storage space which is satisfied by a large number of registers. Some video display generators have their circuitry divided into a decoder(s), RAM(S) and register(s) for handling playfield fixed-object data; and into a decoder-selector(s) and register(s) for handling moving object data.
It is desirable to provide an auxiliary circuit which is intended to be incorporated into a microprocessor based personal computer system, which auxiliary circuit has true microprocessor capabilities, including bit-map data manipulation capabilities, but does not use the space and power of a second microprocessor on the increase in memory needed by the decoder approach, and which can be implemented where inter-chip and backplane wiring is minimized.